assembly - gcc -masm=intel gives me lowercase mnemonics -


compiling simple c program with 

gcc -masm=intel basic.c -o basic.asm

generated assembly below :

.cfi_startproc     push    rbp     .cfi_def_cfa_offset 16     .cfi_offset 6, -16     mov rbp, rsp /i expected mov mov     .cfi_def_cfa_register 6     mov qword ptr [rbp-8], offset flat:.lc0     mov eax, 0     pop rbp /i expected pop pop     .cfi_def_cfa 7, 8     ret     .cfi_endproc

i on intel x86_64 machine , in intel software developer's manual, understand mnemonics represented uppercase (which means suggest using it?).

is there option gcc gives me uppercase mnemonics?

fyi, strip out "noise" in gcc asm output (.cfi directives, unused labels, etc.), see how remove "noise" gcc/clang assembly output?. tl:dr: put code on http://gcc.godbolt.org/

in intel software developer's manual, mnemonics represented uppercase (which means suggest using it?).

i think use all-uppercase alternative code-formatting, can write stuff "performs bitwise , operation" without confusion (because "bitwise , operation" valid english phrase). have gone "perform bitwise and operation", didn't.

their use of all-caps mnemonics , register names is not suggestion it's right way code. intel's tutorials / articles have chunks of asm code (like 1 detecting avx). in listing 1 of that, use lowercase mnemonics , register names except xgetbv, think highlight it, because that's new instruction they're teaching about. intrinsics guide uses lower-case mnemonics in field showing instruction mnemonic maps (compiler optimization can choose different insns...).

mnemonics , register names not case-sensitive. people prefer lower-case. style includes indenting operands consistent column, , same comments, code doesn't ragged. , indent code more labels, can see labels (branch targets). example, bit of the source golfed (smallest code-size) adler-32 in x86-64 machine code illustrates think reasonably style.

    xor     eax,eax         ; scratch reg loading bytes     cdq                     ; edx: high=0     lea     edi, [rdx+1]    ; edi: low=1     ;jrcxz  .end            ; don't handle len=0.  unlike rep, loop checks rcx after decrementing .byteloop:     lodsb                   ; upper 24b of eax stays zeroed (no partial-register stall on intel p6/snb-family cpus, xor-zeroing)     add     edi, eax        ; low += zero_extend(buf[i])     add     edx, edi        ; high += low     loop   .byteloop .end:     ;; exit when ecx = 0, eax = last byte of buf     ;; lodsb @ point load terminating 0 byte, conveniently leaving eax=0

see nasm style guide, linked tag wiki.

is there option gcc gives me uppercase mnemonics?

no. upcase instruction mnemonics , register names sed or if wanted to. (but you'd have careful not munge symbol names, case sensitive).

the pattern-matching in scripts power http://gcc.godbolt.org/ maybe useful this, haven't looked @ js source.


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